On Mon, Nov 18, 2013 at 03:02:24PM +0100, Stanislaw Gruszka wrote: > > The x86 init check whether all booted CPUs have their TSC's synchronized, > > never > > failed so far, however, the tsc clocksource is sporadically marked unstable. > > > > Clocksource tsc unstable (delta = -74994678 ns)
> > Version 00020652: > > Type 0 - Original OEM > > Family 6 - Pentium Pro > > Model 5 - Pentium II Model 5/Xeon/Celeron > > Extended brand string: "Intel(R) Core(TM) i5 CPU 650 @ 3.20GHz" I'm not sure what tool you used to generate that, but its broken, that's model 0x25 (37), it somehow truncates the upper model bits. That said, its a westmere core and I've seen wsm-ep (dual socket) machines loose their TSC sync quite regularly, but this would be the first case a single socket wsm would loose its TSC sync. That leads me to believe your BIOS is screwing you over with SMIs or the like. I would be tempted to say you should simply mark the tsc unstable on boot and live with that -- we fully assume the sched_clock stuff is not going backwards in an 'observable' way. That said, it might be nice to not crash either.. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
