Peter Zijlstra <pet...@infradead.org> writes: Can you please clarify your position on the interleaved buffer?
I still can't see how it is a efficient design. It's generally true in scather-gather (be it software or hardware) that each additional SG entry increases the cost. So to make things efficient you always want to minimize entries as much as possible. >> I don't think the PT design is broken in any way, it's straight >> forward and simple. > > Also, do clarify the other points I asked about. Esp. the non > FREEZE_ON_PMI behaviour of the PT PMI is worrying me immensely. The only reason for hardware freeze is when you have a few entries (like with LBRs) so the interrupt entry code could overwhelm it. But PT is not small, it's gigantic: even with the smallest buffer you have many thousands of entries. So you will get a few branches in the interrupt entry, but it's not a problem because everything you really wanted to trace is still there. Eventually the handler disables PT, so there's no risk of racing with the update or anything like that. Did I miss anything? > To me it seems very weird that PT is hooked to the same PMI as the > normal PMU, it really should have been a different interrupt. It's in the same STATUS register, so it's cheap to check both. It shouldn't add any new spurious problems (or at least nothing worse than what we already have) I understand that it would be nice to separate other NMI users from all of PMI, but that would be an orthogonal problem. Any other issues? -Andi -- a...@linux.intel.com -- Speaking for myself only -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
