Signed-off-by: Daniel
Matuschek <[email protected]>
Existing post_table has duplicate settings for some PLL settings.
Only the first setting was used with mclk_div=1
With the updated post_table, the driver
uses mclk_div=0 whenever it is possible. This allows the WM8804
to work at 256xfs internal clock and only use 128xfs
internal clock for high sample rates where 256xfs is not
supported anymore.
---
sound/soc/codecs/wm8804.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c
index 1704b1e..f605b8b 100644
--- a/sound/soc/codecs/wm8804.c
+++ b/sound/soc/codecs/wm8804.c
@@ -307,9 +307,7 @@ static struct {
unsigned int mclkdiv;
} post_table[] = {
{ 2, 0, 0 },
- { 4, 0, 1 },
{ 4, 1, 0 },
- { 8, 1, 1 },
{ 8, 2, 0 },
{ 16, 2, 1 },
{ 12, 3, 0 },
--
1.7.9.5
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