On Thu, 27 Jan 2005 22:57:25 +0000 Russell King <[EMAIL PROTECTED]> wrote:
> Has e100 actually been fixed to use the PCI DMA API correctly yet? It seems to be doing the right thing. I see the DMA sync calls (properly using cpu vs. device syncing variants) at the right spots, and the only thing the chip really relies upon is ordering of visibility and this is achieved via a combination of cpu memory barriers and the correct DMA sync calls. For example, a pci_dma_sync_single_for_cpu() is always performed before peeking at the descriptors at RX interrupt time (see e100_rx_indicate). When new descriptors are written to, then linked into the chain it memory barriers the cpu writes then DMA syncs the previous descriptor to the device. This is occuring in e100_alloc_skb(). Therefore the only missing sync would be of the new RX descriptor when linking things in like that, ie. at the end of e100_rx_alloc_skb() if rx->prev->skb is non-NULL. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
