On Tue, 18 Feb 2014, carl peng wrote:
Carl, sending the same mail twice within an hour does not speed up
things. It's quite likely that it gets ignored.
> 1. Does it need to implement irq_set_type method in the ioapic_chip
> structure?
No. The irq type is configured by the type of the interrupt or the
BIOS.
ISA interrupts are always polarity zero edge triggered (historic)
PCI interrupts are always polarity one level triggered
PCIE interrupts are either legacy PCI or with MSI[X] always edge
triggered
> 2. if no need to implement it, how can device driver set the trigger mode
> of APIC interrupt controller pin?
Not at all.
The device which is connected to one of the busses must follow the
specification of the bus. There is no choice. Any additional
requirements of the device to deal with external signals must be
handled by the device itself and converted to the appropriate bus
requirement.
This all is configured by the kernel automatically through bus
detection and BIOS tables.
Thanks,
tglx
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