On few architectures, there are few restrictions on DMAble area of system
RAM. That also means that devices needs to know about this restrictions so
that the dma_masks can be updated accordingly and dma address translation
helpers can add/subtract the dma offset.
In most of cases DMA addresses can be performed using offset value of
Bus address space relatively to physical address space as following:
PFN->DMA: __pfn_to_phys(pfn + [-]dma_pfn_offset)
DMA->PFN: __phys_to_pfn(dma_addr) + [-]dma_pfn_offset
So we introduce per device dma_pfn_offset which can be popullated
by architectures init code while creating the devices.
Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Cc: Russell King <li...@arm.linux.org.uk>
Cc: Arnd Bergmann <a...@arndb.de>
Cc: Olof Johansson <o...@lixom.net>
Cc: Grant Likely <grant.lik...@linaro.org>
Cc: Rob Herring <robh...@kernel.org>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Linus Walleij <linus.wall...@linaro.org>
Signed-off-by: Grygorii Strashko <grygorii.stras...@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilim...@ti.com>
---
include/linux/device.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/device.h b/include/linux/device.h
index 952b010..6940b25 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -688,6 +688,7 @@ struct acpi_dev_node {
* @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all
* hardware supports 64-bit addresses for consistent allocations
* such descriptors.
+ * @dma_pfn_offset: offset of DMA memory range relatively of RAM
* @dma_parms: A low level driver may set these to teach IOMMU code about
* segment limitations.
* @dma_pools: Dma pools (if dma'ble device).
@@ -753,6 +754,7 @@ struct device {
not all hardware supports
64 bit addresses for consistent
allocations such descriptors. */
+ unsigned long dma_pfn_offset;
struct device_dma_parameters *dma_parms;
--
1.7.9.5
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