From: Srinivas Kandagatla <[email protected]> This patch adds a 3 clock cycle delay required after writing to controller registers on Qualcomm SOCs. Without this delay cards are either not detected or fails as soon as card is put into data transfer mode.
Signed-off-by: Srinivas Kandagatla <[email protected]> --- drivers/mmc/host/mmci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 86bf330..2dc7581 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -168,6 +168,7 @@ static struct variant_data variant_qcom = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, + .reg_write_delay = 3, .blksz_datactrl4 = true, .datalength_bits = 24, .blksz_datactrl4 = true, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
