3.2.58-rc1 review patch. If anyone has any objections, please let me know.
------------------ From: Huacai Chen <che...@lemote.com> commit c14af233fbe279d0e561ecf84f1208b1bae087ef upstream. The original MIPS hibernate code flushes cache and TLB entries in swsusp_arch_resume(). But they are removed in Commit 44eeab67416711 (MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross- CPU flush is surely unnecessary because all but the local CPU have already been disabled. But a local flush (at least the TLB flush) is needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is very easy to produce a kernel panic (kernel page fault, or unaligned access). The root cause is E1000E driver use vzalloc_node() to allocate pages, the stale TLB entries of the booting kernel will be misused by the resumed target kernel. Signed-off-by: Huacai Chen <che...@lemote.com> Cc: John Crispin <j...@phrozen.org> Cc: Steven J. Hill <steven.h...@imgtec.com> Cc: Aurelien Jarno <aurel...@aurel32.net> Cc: linux-m...@linux-mips.org Cc: Fuxin Zhang <zhan...@lemote.com> Cc: Zhangjin Wu <wuzhang...@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6643/ Signed-off-by: Ralf Baechle <r...@linux-mips.org> Signed-off-by: Ben Hutchings <b...@decadent.org.uk> --- arch/mips/power/hibernate.S | 1 + 1 file changed, 1 insertion(+) --- a/arch/mips/power/hibernate.S +++ b/arch/mips/power/hibernate.S @@ -44,6 +44,7 @@ LEAF(swsusp_arch_resume) bne t1, t3, 1b PTR_L t0, PBE_NEXT(t0) bnez t0, 0b + jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */ PTR_LA t0, saved_regs PTR_L ra, PT_R31(t0) PTR_L sp, PT_R29(t0) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
