Il 17/04/2014 00:04, Marcelo Tosatti ha scritto:
> >> @@ -3550,9 +3550,9 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu,
> >> break;
> >> case PT64_ROOT_LEVEL:
> >> context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
> >> - rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
> >> + rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7);
> >> context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
> >> - rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
> >> + rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7);
> >
> > Bit 7 is not reserved either, for the PDPTE (its PageSize bit).
> >
>
> In long mode (IA-32e), bit 7 is definitely reserved.
It's always reserved for PML4E (rsvd_bits_mask[x][3]), while for PDPTEs
it is not reserved if you have 1GB pages.
There is a separate reserved mask for PS=1, nevermind.
Yeah, but the situation for IA32e rsvd_bits_mask[0][2] is exactly the
same as for PAE rsvd_bits_mask[0][1], and we're not marking the bit as
reserved there.
The right thing to do is to add rsvd_bits(7, 7) to both
rsvd_bits_mask[0][2] and rsvd_bits_mask[1][2], if 1GB pages are not
supported.
As written, the patch has no effect on PDPTEs because
rsvd_bits_mask[0][2] is only accessed if bit 7 is zero.
Nadav, would you mind preparing a follow-up? Also, how did you find
these issues and test the fixes?
Paolo
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