On Wed, May 07, 2014 at 06:20:49PM +0200, Boris BREZILLON wrote:
> The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
> mask all interrupts no matter what IMR claims about already masked irqs.
Crap, I totally forgot about this. Doug reported the problem off-list
back in December, but it got lost somehow. Sorry.
> Signed-off-by: Boris BREZILLON <boris.brezil...@free-electrons.com>
> Reported-by: Bryan Evenson <beven...@melinkcorp.com>
> ---
> Hello Bryan,
>
> Yet another patch for you ;-).
>
> As usual, could you tell me if it fixes your bug.
>
> BTW, thanks for your tests.
>
> Best Regards,
>
> Boris
>
> arch/arm/mach-at91/sysirq_mask.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-at91/sysirq_mask.c
> b/arch/arm/mach-at91/sysirq_mask.c
> index 2ba694f..eb3d2a5 100644
> --- a/arch/arm/mach-at91/sysirq_mask.c
> +++ b/arch/arm/mach-at91/sysirq_mask.c
> @@ -37,12 +37,7 @@ void __init at91_sysirq_mask_rtc(u32 rtc_base)
> if (!base)
> return;
>
> - mask = readl_relaxed(base + AT91_RTC_IMR);
> - if (mask) {
> - pr_info("AT91: Disabling rtc irq\n");
> - writel_relaxed(mask, base + AT91_RTC_IDR);
> - (void)readl_relaxed(base + AT91_RTC_IMR); /* flush */
> - }
> + writel_relaxed(0x1f, base + AT91_RTC_IDR);
I believe this is the right way to handle this hardware bug (IMR is
always read as 0 on one particular SoC), but please document this in a
comment.
You should also keep the flush (read of IMR) regardless (to make sure
the write has reached the peripheral), and remember to remove the now
unused mask variable.
> iounmap(base);
> }
Thanks,
Johan
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