Hi Kishon,
On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
> Added missing 32khz clock used by PCIe PHY.
> The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Typo in $subject
s/clocks/clock
--
cheers,
-roger
>
> Cc: Tony Lindgren <t...@atomide.com>
> Cc: Rajendra Nayak <rna...@ti.com>
> Cc: Tero Kristo <t-kri...@ti.com>
> Cc: Paul Walmsley <p...@pwsan.com>
> Cc: Rob Herring <robh...@kernel.org>
> Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
> ---
> arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> index 44993ec..e1bd052 100644
> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> @@ -1165,6 +1165,14 @@
> reg = <0x021c>, <0x0220>;
> };
>
> + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
> + compatible = "ti,gate-clock";
> + clocks = <&sys_32k_ck>;
> + #clock-cells = <0>;
> + reg = <0x13b0>;
> + ti,bit-shift = <8>;
> + };
> +
> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
> compatible = "ti,divider-clock";
> clocks = <&apll_pcie_ck>;
>
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