On Thu, May 15, 2014 at 4:32 PM, Andi Kleen <a...@linux.intel.com> wrote: > On Thu, May 15, 2014 at 01:53:37PM +0200, Stephane Eranian wrote: >> >> This patches fixes a bug in precise_store_data_hsw() whereby >> it would set the data source memory level to the wrong value. >> >> As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear >> Address Information in PEBS Record), when status bit 0 is set >> this is a L1 hit, otherwise this is a L1 miss. >> >> This patch encodes the memory level according to the specification. > > It's not enough. as I said it needs more fixes. > > For most events it should be _NA, _STORE can be only specified > for the explicit _STORE events. > Yes, I forgot about that. Will re-spin the patch.
> -Andi > >> >> Signed-off-by: Stephane Eranian <eran...@google.com> >> >> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c >> b/arch/x86/kernel/cpu/perf_event_intel_ds.c >> index ae96cfa..81424f6 100644 >> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c >> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c >> @@ -114,9 +114,13 @@ static u64 precise_store_data_hsw(u64 status) >> >> dse.val = 0; >> dse.mem_op = PERF_MEM_OP_STORE; >> - dse.mem_lvl = PERF_MEM_LVL_NA; >> + dse.mem_lvl = PERF_MEM_LVL_L1; >> + >> if (status & 1) >> - dse.mem_lvl = PERF_MEM_LVL_L1; >> + dse.mem_lvl |= PERF_MEM_LVL_HIT; >> + else >> + dse.mem_lvl |= PERF_MEM_LVL_MISS; >> + >> /* Nothing else supported. Sorry. */ >> return dse.val; >> } > > -- > a...@linux.intel.com -- Speaking for myself only -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
