On Thu, May 22, 2014 at 07:18:38PM +0100, Sam Ravnborg wrote:
> On Thu, May 22, 2014 at 05:47:26PM +0100, Will Deacon wrote:
> > write{b,w,l,q}_relaxed are implemented by some architectures in order to
> > permit memory-mapped I/O accesses with weaker barrier semantics than the
> > non-relaxed variants.
> >
> > This patch adds dummy macros for the write accessors to sparc, in the
> > same vein as the dummy definitions for the relaxed read accessors. The
> > existing relaxed read{b,w,l} accessors are moved into asm/io.h, since
> > they are identical between 32-bit and 64-bit machines.
> >
> > Cc: "David S. Miller" <da...@davemloft.net>
> > Signed-off-by: Will Deacon <will.dea...@arm.com>
> Look good:
> Acked-by: Sam Ravnborg <s...@ravnborg.org>
Thanks, Sam.
> But you should wait for David's ack too.
Yeah, I still need to get buy-in on the semantics from the PPC folks
anyway.
Will
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