On Mon, Jun 02, 2014 at 04:46:32PM -0400, Mikulas Patocka wrote: > It's not only parisc - tile32, arc, metag (maybe hexagon) are broken too, > because they don't have cmpxchg in hardware.
metag actually does, and the lock1 thing is a fallback/test thing:
config METAG_ATOMICITY_LOCK1
depends on SMP
bool "lock1"
help
This option uses the LOCK1 instruction for atomicity. This is mainly
provided as a debugging aid if the lnkget/lnkset atomicity primitive
isn't working properly.
Then again, metag has qualiteee bits like:
config METAG_SMP_WRITE_REORDERING
bool
help
This attempts to prevent cache-memory incoherence due to external
reordering of writes from different hardware threads when SMP is
enabled. It adds fences (system event 0) to smp_mb and smp_rmb in an
attempt to catch some of the cases, and also before writes to shared
memory in LOCK1 protected atomics and spinlocks.
This will not completely prevent cache incoherency on affected cores.
Which makes me back away slowly before starting to run.
And there is sane arc hardware:
config ARC_HAS_LLSC
bool "Insn: LLOCK/SCOND (efficient atomic ops)"
default y
depends on ARC_CPU_770 && !ARC_CANT_LLSC
tile32 is indeed equally wrecked, but at least they have a tile64 system
that is useful (albeit somewhat strange).
Same for sparc32, there's sparc64 which is sane.
parisc otoh is a dead arch that never got sane.
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