On Thu, Jun 19, 2014 at 05:58:29PM +0200, Stephane Eranian wrote: > The load latency does not have to be constrained to counter 3 > on any of SNB, IVB, HSW. It operates fine on any PEBS-capable > counter. > > The precise store event for SNB, IVB needs to be on counter 3. > But on Haswell, precise store is implemented differently and > the constraint is not needed anymore, so we remove it.
Looks good to me. -Andi -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
