Patch 3 of 3:
Signed-off-by: Sreenivas Bagalkote <[EMAIL PROTECTED]>
diff -Naur linux-2.6.11-orig/drivers/scsi/megaraid/megaraid_sas.h
linux-2.6.11/drivers/scsi/megaraid/megaraid_sas.h
--- linux-2.6.11-orig/drivers/scsi/megaraid/megaraid_sas.h 1969-12-31
19:00:00.000000000 -0500
+++ linux-2.6.11/drivers/scsi/megaraid/megaraid_sas.h 2005-03-05
21:41:25.503377336 -0500
@@ -0,0 +1,1118 @@
+/*
+ *
+ * Linux MegaRAID driver for SAS based RAID controllers
+ *
+ * Copyright (c) 2003-2005 LSI Logic Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * FILE : megaraid_sas.h
+ */
+
+#ifndef LSI_MEGARAID_SAS_H
+#define LSI_MEGARAID_SAS_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/list.h>
+#include <linux/version.h>
+#include <linux/moduleparam.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+
+#include <scsi/scsi.h>
+#include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_device.h>
+#include <scsi/scsi_host.h>
+
+/**
+ * MegaRAID SAS Driver meta data
+ */
+#define MEGASAS_VERSION "00.00.01.00"
+#define MEGASAS_RELDATE "Mar 05, 2005"
+#define MEGASAS_EXT_VERSION ""
+
+/**
+ * MegaRAID SAS supported controllers
+ */
+#define PCI_DEVICE_LSI_1064 0x0411
+#define PCI_SUBVENDOR_x0000 0x0000
+#define PCI_SUBVENDOR_x1000 0x1000
+#define PCI_SUBSYSTEM_x0000 0x0000
+#define PCI_SUBSYSTEM_x0001 0x0001
+#define PCI_SUBSYSTEM_x0002 0x0002
+#define PCI_SUBSYSTEM_x1001 0x1001
+
+#define PCI_DEVICE_ID_PERC5 0x0015
+#define PCI_SUBSYSTEM_PERC5H 0x1F01
+#define PCI_SUBSYSTEM_PERC5L 0x1F02
+#define PCI_SUBSYSTEM_PERC5I 0x1F03
+
+#define PCI_SUB_DEVICEID_FSC 0x1081
+#define PCI_SUB_VENDORID_FSC 0x1734
+/*
+ * =====================================
+ * MegaRAID SAS MFI firmware definitions
+ * =====================================
+ */
+
+/**
+ * FW posts its state in upper 4 bits of outbound_msg_0 register
+ */
+#define MFI_STATE_MASK 0xF0000000
+#define MFI_STATE_UNDEFINED 0x00000000
+#define MFI_STATE_BB_INIT 0x10000000
+#define MFI_STATE_FW_INIT 0x40000000
+#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
+#define MFI_STATE_DEVICE_SCAN 0x80000000
+#define MFI_STATE_READY 0xB0000000
+#define MFI_STATE_OPERATIONAL 0xC0000000
+#define MFI_STATE_FAULT 0xF0000000
+
+#define MEGAMFI_FRAME_SIZE 64
+
+/**
+ * During FW init, clear pending cmds & reset state using inbound_msg_0
+ *
+ * ABORT : Abort all pending cmds
+ * READY : Move from OPERATIONAL to READY state; discard queue info
+ * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
+ * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
+ */
+#define MFI_INIT_ABORT 0x00000000
+#define MFI_INIT_READY 0x00000002
+#define MFI_INIT_MFIMODE 0x00000004
+#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
+#define MFI_RESET_FLAGS
MFI_INIT_READY|MFI_INIT_MFIMODE
+
+/**
+ * MFI frame flags
+ */
+#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
+#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
+#define MFI_FRAME_SGL32 0x0000
+#define MFI_FRAME_SGL64 0x0002
+#define MFI_FRAME_SENSE32 0x0000
+#define MFI_FRAME_SENSE64 0x0004
+#define MFI_FRAME_DIR_NONE 0x0000
+#define MFI_FRAME_DIR_WRITE 0x0008
+#define MFI_FRAME_DIR_READ 0x0010
+#define MFI_FRAME_DIR_BOTH 0x0018
+
+/**
+ * Definition for cmd_status
+ */
+#define MFI_CMD_STATUS_POLL_MODE 0xFF
+
+/**
+ * MFI command opcodes
+ */
+#define MFI_CMD_INIT 0x00
+#define MFI_CMD_LD_READ 0x01
+#define MFI_CMD_LD_WRITE 0x02
+#define MFI_CMD_LD_SCSI_IO 0x03
+#define MFI_CMD_PD_SCSI_IO 0x04
+#define MFI_CMD_DCMD 0x05
+#define MFI_CMD_ABORT 0x06
+#define MFI_CMD_SMP 0x07
+#define MFI_CMD_STP 0x08
+
+#define MR_DCMD_CTRL_GET_INFO 0x01010000
+
+#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
+#define MR_FLUSH_CTRL_CACHE 0x01
+#define MR_FLUSH_DISK_CACHE 0x02
+
+#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
+#define MR_ENABLE_DRIVE_SPINDOWN 0x01
+
+#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
+#define MR_DCMD_CTRL_EVENT_GET 0x01040300
+#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
+#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
+
+/**
+ * MFI command completion codes
+ */
+enum MFI_STAT {
+ MFI_STAT_OK = 0x00,
+ MFI_STAT_INVALID_CMD = 0x01,
+ MFI_STAT_INVALID_DCMD = 0x02,
+ MFI_STAT_INVALID_PARAMETER = 0x03,
+ MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
+ MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
+ MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
+ MFI_STAT_APP_IN_USE = 0x07,
+ MFI_STAT_APP_NOT_INITIALIZED = 0x08,
+ MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
+ MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
+ MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
+ MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
+ MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
+ MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
+ MFI_STAT_FLASH_BUSY = 0x0f,
+ MFI_STAT_FLASH_ERROR = 0x10,
+ MFI_STAT_FLASH_IMAGE_BAD = 0x11,
+ MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
+ MFI_STAT_FLASH_NOT_OPEN = 0x13,
+ MFI_STAT_FLASH_NOT_STARTED = 0x14,
+ MFI_STAT_FLUSH_FAILED = 0x15,
+ MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
+ MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
+ MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
+ MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
+ MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
+ MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
+ MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
+ MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
+ MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
+ MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
+ MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
+ MFI_STAT_MFC_HW_ERROR = 0x21,
+ MFI_STAT_NO_HW_PRESENT = 0x22,
+ MFI_STAT_NOT_FOUND = 0x23,
+ MFI_STAT_NOT_IN_ENCL = 0x24,
+ MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
+ MFI_STAT_PD_TYPE_WRONG = 0x26,
+ MFI_STAT_PR_DISABLED = 0x27,
+ MFI_STAT_ROW_INDEX_INVALID = 0x28,
+ MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
+ MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
+ MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
+ MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
+ MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
+ MFI_STAT_SCSI_IO_FAILED = 0x2e,
+ MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
+ MFI_STAT_SHUTDOWN_FAILED = 0x30,
+ MFI_STAT_TIME_NOT_SET = 0x31,
+ MFI_STAT_WRONG_STATE = 0x32,
+ MFI_STAT_INVALID_STATUS = 0xFF
+
+};
+
+enum MR_EVT_CLASS {
+
+ MR_EVT_CLASS_DEBUG = -2,
+ MR_EVT_CLASS_PROGRESS = -1,
+ MR_EVT_CLASS_INFO = 0,
+ MR_EVT_CLASS_WARNING = 1,
+ MR_EVT_CLASS_CRITICAL = 2,
+ MR_EVT_CLASS_FATAL = 3,
+ MR_EVT_CLASS_DEAD = 4,
+
+};
+
+enum MR_EVT_LOCALE{
+
+ MR_EVT_LOCALE_LD = 0x0001,
+ MR_EVT_LOCALE_PD = 0x0002,
+ MR_EVT_LOCALE_ENCL = 0x0004,
+ MR_EVT_LOCALE_BBU = 0x0008,
+ MR_EVT_LOCALE_SAS = 0x0010,
+ MR_EVT_LOCALE_CTRL = 0x0020,
+ MR_EVT_LOCALE_CONFIG = 0x0040,
+ MR_EVT_LOCALE_CLUSTER = 0x0080,
+ MR_EVT_LOCALE_ALL = 0xffff,
+
+};
+
+enum MR_EVT_ARGS {
+
+ MR_EVT_ARGS_NONE,
+ MR_EVT_ARGS_CDB_SENSE,
+ MR_EVT_ARGS_LD,
+ MR_EVT_ARGS_LD_COUNT,
+ MR_EVT_ARGS_LD_LBA,
+ MR_EVT_ARGS_LD_OWNER,
+ MR_EVT_ARGS_LD_LBA_PD_LBA,
+ MR_EVT_ARGS_LD_PROG,
+ MR_EVT_ARGS_LD_STATE,
+ MR_EVT_ARGS_LD_STRIP,
+ MR_EVT_ARGS_PD,
+ MR_EVT_ARGS_PD_ERR,
+ MR_EVT_ARGS_PD_LBA,
+ MR_EVT_ARGS_PD_LBA_LD,
+ MR_EVT_ARGS_PD_PROG,
+ MR_EVT_ARGS_PD_STATE,
+ MR_EVT_ARGS_PCI,
+ MR_EVT_ARGS_RATE,
+ MR_EVT_ARGS_STR,
+ MR_EVT_ARGS_TIME,
+ MR_EVT_ARGS_ECC,
+
+};
+
+/*
+ * SAS controller properties
+ */
+struct megasas_ctrl_prop {
+
+ uint16_t seq_num;
+ uint16_t pred_fail_poll_interval;
+ uint16_t intr_throttle_count;
+ uint16_t intr_throttle_timeouts;
+
+ uint8_t rebuild_rate;
+ uint8_t patrol_read_rate;
+ uint8_t bgi_rate;
+ uint8_t cc_rate;
+ uint8_t recon_rate;
+
+ uint8_t cache_flush_interval;
+
+ uint8_t spinup_drv_count;
+ uint8_t spinup_delay;
+
+ uint8_t cluster_enable;
+ uint8_t coercion_mode;
+ uint8_t disk_write_cache_disable;
+ uint8_t alarm_enable;
+
+ uint8_t reserved[44];
+
+} __attribute__ ((packed));
+
+/*
+ * SAS controller information
+ */
+struct megasas_ctrl_info {
+
+ /*
+ * PCI device information
+ */
+ struct {
+
+ uint16_t vendor_id;
+ uint16_t device_id;
+ uint16_t sub_vendor_id;
+ uint16_t sub_device_id;
+ uint8_t reserved[24];
+
+ } __attribute__ ((packed)) pci;
+
+ /*
+ * Host interface information
+ */
+ struct {
+
+ uint8_t PCIX : 1;
+ uint8_t PCIE : 1;
+ uint8_t iSCSI : 1;
+ uint8_t SAS_3G : 1;
+ uint8_t reserved_0 : 4;
+ uint8_t reserved_1[6];
+ uint8_t port_count;
+ uint64_t port_addr[8];
+
+ } __attribute__ ((packed)) host_interface;
+
+ /*
+ * Device (backend) interface information
+ */
+ struct {
+
+ uint8_t SPI : 1;
+ uint8_t SAS_3G : 1;
+ uint8_t SATA_1_5G : 1;
+ uint8_t SATA_3G : 1;
+ uint8_t reserved_0 : 4;
+ uint8_t reserved_1[6];
+ uint8_t port_count;
+ uint64_t port_addr[8];
+
+ } __attribute__ ((packed)) device_interface;
+
+ /*
+ * List of components residing in flash. All str are null terminated
+ */
+ uint32_t image_check_word;
+ uint32_t image_component_count;
+
+ struct {
+
+ char name[8];
+ char version[32];
+ char build_date[16];
+ char built_time[16];
+
+ } __attribute__ ((packed)) image_component[8];
+
+ /*
+ * List of flash components that have been flashed on the card, but
+ * are not in use, pending reset of the adapter. This list will be
+ * empty if a flash operation has not occurred. All stings are null
+ * terminated
+ */
+ uint32_t pending_image_component_count;
+
+ struct {
+
+ char name[8];
+ char version[32];
+ char build_date[16];
+ char build_time[16];
+
+ } __attribute__ ((packed)) pending_image_component[8];
+
+ uint8_t max_arms;
+ uint8_t max_spans;
+ uint8_t max_arrays;
+ uint8_t max_lds;
+
+ char product_name[80];
+ char serial_no[32];
+
+ /*
+ * Other physical/controller/operation information. Indicates the
+ * presence of the hardware
+ */
+ struct {
+
+ uint32_t bbu : 1;
+ uint32_t alarm : 1;
+ uint32_t nvram : 1;
+ uint32_t uart : 1;
+ uint32_t reserved : 28;
+
+ } __attribute__ ((packed)) hw_present;
+
+ uint32_t current_fw_time;
+
+ /*
+ * Maximum data transfer sizes
+ */
+ uint16_t max_concurrent_cmds;
+ uint16_t max_sge_count;
+ uint32_t max_request_size;
+
+ /*
+ * Logical and physical device counts
+ */
+ uint16_t ld_present_count;
+ uint16_t ld_degraded_count;
+ uint16_t ld_offline_count;
+
+ uint16_t pd_present_count;
+ uint16_t pd_disk_present_count;
+ uint16_t pd_disk_pred_failure_count;
+ uint16_t pd_disk_failed_count;
+
+ /*
+ * Memory size information
+ */
+ uint16_t nvram_size;
+ uint16_t memory_size;
+ uint16_t flash_size;
+
+ /*
+ * Error counters
+ */
+ uint16_t mem_correctable_error_count;
+ uint16_t mem_uncorrectable_error_count;
+
+ /*
+ * Cluster information
+ */
+ uint8_t cluster_permitted;
+ uint8_t cluster_active;
+ uint8_t reserved_1[2];
+
+ /*
+ * Controller capabilities structures
+ */
+ struct {
+
+ uint32_t raid_level_0 : 1;
+ uint32_t raid_level_1 : 1;
+ uint32_t raid_level_5 : 1;
+ uint32_t raid_level_1E : 1;
+ uint32_t reserved : 28;
+
+ } __attribute__ ((packed)) raid_levels;
+
+ struct {
+
+ uint32_t rbld_rate : 1;
+ uint32_t cc_rate : 1;
+ uint32_t bgi_rate : 1;
+ uint32_t recon_rate : 1;
+ uint32_t patrol_rate : 1;
+ uint32_t alarm_control : 1;
+ uint32_t cluster_supported : 1;
+ uint32_t bbu : 1;
+ uint32_t spanning_allowed : 1;
+ uint32_t dedicated_hotspares : 1;
+ uint32_t revertible_hotspares : 1;
+ uint32_t foreign_config_import : 1;
+ uint32_t self_diagnostic : 1;
+ uint32_t reserved : 19;
+
+ } __attribute__ ((packed)) adapter_operations;
+
+ struct {
+
+ uint32_t read_policy : 1;
+ uint32_t write_policy : 1;
+ uint32_t io_policy : 1;
+ uint32_t access_policy : 1;
+ uint32_t reserved : 28;
+
+ } __attribute__ ((packed)) ld_operations;
+
+ struct {
+
+ uint8_t min;
+ uint8_t max;
+ uint8_t reserved[2];
+
+ } __attribute__ ((packed)) stripe_size_operations;
+
+ struct {
+
+ uint32_t force_online : 1;
+ uint32_t force_offline : 1;
+ uint32_t force_rebuild : 1;
+ uint32_t reserved : 29;
+
+ } __attribute__ ((packed)) pd_operations;
+
+ struct {
+
+ uint32_t ctrl_supports_sas : 1;
+ uint32_t ctrl_supports_sata : 1;
+ uint32_t allow_mix_in_encl : 1;
+ uint32_t allow_mix_in_ld : 1;
+ uint32_t allow_sata_in_cluster : 1;
+ uint32_t reserved : 27;
+
+ } __attribute__ ((packed)) pd_mix_support;
+
+ /*
+ * Include the controller properties (changeable items)
+ */
+ uint8_t reserved_2[12];
+ struct megasas_ctrl_prop properties;
+
+ uint8_t pad[0x800 - 0x640];
+
+} __attribute__ ((packed));
+
+/*
+ * ===============================
+ * MegaRAID SAS driver definitions
+ * ===============================
+ */
+
+
+#define MEGADRV_MAX_NUM_CMD 1024
+
+#define MEGADRV_MAX_PD_CHANNELS 2
+#define MEGADRV_MAX_LD_CHANNELS 2
+#define MEGADRV_MAX_CHANNELS (MEGADRV_MAX_PD_CHANNELS + \
+ MEGADRV_MAX_LD_CHANNELS)
+#define MEGADRV_MAX_DEV_PER_CHANNEL 128
+#define MEGADRV_DEFAULT_INIT_ID -1
+#define MEGADRV_MAX_CMD_PER_LUN 1000
+#define MEGADRV_MAX_LUN 8
+#define MEGADRV_MAX_LD 64
+
+#define MEGADRV_RESET_WAIT_TIME 300
+#define MEGADRV_RESET_NOTICE_INTERVAL 5
+
+/*
+ * All MFI register set macros accept megasas_register_set*
+ */
+#define RD_OB_MSG_0(regs) readl((void*)(&(regs)->outbound_msg_0))
+#define WR_IN_MSG_0(v, regs) writel((v),(void*)(&(regs)->inbound_msg_0))
+#define WR_IN_DOORBELL(v, regs)
writel((v),(void*)(&(regs)->inbound_doorbell))
+#define WR_IN_QPORT(v, regs)
writel((v),(void*)(&(regs)->inbound_queue_port))
+
+#define RD_OB_INTR_STATUS(regs)
readl((void*)(&(regs)->outbound_intr_status))
+#define WR_OB_INTR_STATUS(v, regs)
writel((v),(&(regs)->outbound_intr_status))
+
+/*
+ * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
+ * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
+ * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
+ */
+#define MFI_MAX_SUPP_CMDS(regs) ((RD_OB_MSG_0(regs)) & 0x00FFFF)
+#define MFI_MAX_SUPP_SGES(regs) (((RD_OB_MSG_0(regs)) & 0x0FF0000)
>> 0x10)
+#define MFI_M64_ENABLED(regs) ((RD_OB_MSG_0(regs)) & 0x1000000)
+
+#define MFI_OB_INTR_STATUS_MASK 0x00000002
+#define MFI_POLL_TIMEOUT_SECS 10
+
+#define MFI_ENABLE_INTR(regs)
writel(1,(void*)(&(regs)->outbound_intr_mask))
+
+#define MFI_DISABLE_INTR(regs) \
+{ \
+ uint32_t disable = ~0x00000001; \
+ uint32_t mask = readl((void*)(&(regs)->outbound_intr_mask)); \
+ mask &= disable; \
+ writel(mask, (void*)(&(regs)->outbound_intr_mask)); \
+}
+
+
+struct megasas_register_set {
+
+ uint32_t reserved_0[4]; /*0000h*/
+
+ uint32_t inbound_msg_0; /*0010h*/
+ uint32_t inbound_msg_1; /*0014h*/
+ uint32_t outbound_msg_0; /*0018h*/
+ uint32_t outbound_msg_1; /*001Ch*/
+
+ uint32_t inbound_doorbell; /*0020h*/
+ uint32_t inbound_intr_status; /*0024h*/
+ uint32_t inbound_intr_mask; /*0028h*/
+
+ uint32_t outbound_doorbell; /*002Ch*/
+ uint32_t outbound_intr_status; /*0030h*/
+ uint32_t outbound_intr_mask; /*0034h*/
+
+ uint32_t reserved_1[2]; /*0038h*/
+
+ uint32_t inbound_queue_port; /*0040h*/
+ uint32_t outbound_queue_port; /*0044h*/
+
+ uint32_t reserved_2; /*004Ch*/
+
+ uint32_t index_registers[1004]; /*0050h*/
+
+} __attribute__ ((packed));
+
+struct megasas_sge32 {
+
+ uint32_t phys_addr;
+ uint32_t length;
+
+} __attribute__ ((packed));
+
+struct megasas_sge64 {
+
+ uint64_t phys_addr;
+ uint32_t length;
+
+} __attribute__ ((packed));
+
+union megasas_sgl {
+
+ struct megasas_sge32 sge32[1];
+ struct megasas_sge64 sge64[1];
+
+} __attribute__ ((packed));
+
+struct megasas_header {
+
+ uint8_t cmd; /*00h*/
+ uint8_t sense_len; /*01h*/
+ uint8_t cmd_status; /*02h*/
+ uint8_t scsi_status; /*03h*/
+
+ uint8_t target_id; /*04h*/
+ uint8_t lun; /*05h*/
+ uint8_t cdb_len; /*06h*/
+ uint8_t sge_count; /*07h*/
+
+ uint32_t context; /*08h*/
+ uint32_t pad_0; /*0Ch*/
+
+ uint16_t flags; /*10h*/
+ uint16_t timeout; /*12h*/
+ uint32_t data_xferlen; /*14h*/
+
+} __attribute__ ((packed));
+
+union megasas_sgl_frame {
+
+ struct megasas_sge32 sge32[8];
+ struct megasas_sge64 sge64[5];
+
+} __attribute__ ((packed));
+
+struct megasas_init_frame {
+
+ uint8_t cmd; /*00h*/
+ uint8_t reserved_0; /*01h*/
+ uint8_t cmd_status; /*02h*/
+
+ uint8_t reserved_1; /*03h*/
+ uint32_t reserved_2; /*04h*/
+
+ uint32_t context; /*08h*/
+ uint32_t pad_0; /*0Ch*/
+
+ uint16_t flags; /*10h*/
+ uint16_t reserved_3; /*12h*/
+ uint32_t data_xfer_len; /*14h*/
+
+ uint32_t queue_info_new_phys_addr_lo; /*18h*/
+ uint32_t queue_info_new_phys_addr_hi; /*1Ch*/
+ uint32_t queue_info_old_phys_addr_lo; /*20h*/
+ uint32_t queue_info_old_phys_addr_hi; /*24h*/
+
+ uint32_t reserved_4[6]; /*28h*/
+
+} __attribute__ ((packed));
+
+struct megasas_init_queue_info {
+
+ uint32_t init_flags; /*00h*/
+ uint32_t reply_queue_entries; /*04h*/
+
+ uint32_t reply_queue_start_phys_addr_lo; /*08h*/
+ uint32_t reply_queue_start_phys_addr_hi; /*0Ch*/
+ uint32_t producer_index_phys_addr_lo; /*10h*/
+ uint32_t producer_index_phys_addr_hi; /*14h*/
+ uint32_t consumer_index_phys_addr_lo; /*18h*/
+ uint32_t consumer_index_phys_addr_hi; /*1Ch*/
+
+} __attribute__ ((packed));
+
+struct megasas_io_frame {
+
+ uint8_t cmd; /*00h*/
+ uint8_t sense_len; /*01h*/
+ uint8_t cmd_status; /*02h*/
+ uint8_t scsi_status; /*03h*/
+
+ uint8_t target_id; /*04h*/
+ uint8_t access_byte; /*05h*/
+ uint8_t reserved_0; /*06h*/
+ uint8_t sge_count; /*07h*/
+
+ uint32_t context; /*08h*/
+ uint32_t pad_0; /*0Ch*/
+
+ uint16_t flags; /*10h*/
+ uint16_t timeout; /*12h*/
+ uint32_t lba_count; /*14h*/
+
+ uint32_t sense_buf_phys_addr_lo; /*18h*/
+ uint32_t sense_buf_phys_addr_hi; /*1Ch*/
+
+ unsigned long start_lba_lo; /*20h*/
+ unsigned long start_lba_hi; /*24h*/
+
+ union megasas_sgl sgl; /*28h*/
+
+} __attribute__ ((packed));
+
+struct megasas_pthru_frame {
+
+ uint8_t cmd; /*00h*/
+ uint8_t sense_len; /*01h*/
+ uint8_t cmd_status; /*02h*/
+ uint8_t scsi_status; /*03h*/
+
+ uint8_t target_id; /*04h*/
+ uint8_t lun; /*05h*/
+ uint8_t cdb_len; /*06h*/
+ uint8_t sge_count; /*07h*/
+
+ uint32_t context; /*08h*/
+ uint32_t pad_0; /*0Ch*/
+
+ uint16_t flags; /*10h*/
+ uint16_t timeout; /*12h*/
+ uint32_t data_xfer_len; /*14h*/
+
+ uint32_t sense_buf_phys_addr_lo; /*18h*/
+ uint32_t sense_buf_phys_addr_hi; /*1Ch*/
+
+ uint8_t cdb[16]; /*20h*/
+ union megasas_sgl sgl; /*30h*/
+
+} __attribute__ ((packed));
+
+struct megasas_dcmd_frame {
+
+ uint8_t cmd; /*00h*/
+ uint8_t reserved_0; /*01h*/
+ uint8_t cmd_status; /*02h*/
+ uint8_t reserved_1[4]; /*03h*/
+ uint8_t sge_count; /*07h*/
+
+ uint32_t context; /*08h*/
+ uint32_t pad_0; /*0Ch*/
+
+ uint16_t flags; /*10h*/
+ uint16_t timeout; /*12h*/
+
+ uint32_t data_xfer_len; /*14h*/
+ uint32_t opcode; /*18h*/
+
+ uint8_t mbox[12]; /*1Ch*/
+
+ union megasas_sgl sgl; /*28h*/
+
+} __attribute__ ((packed));
+
+struct megasas_abort_frame {
+
+ uint8_t cmd; /*00h*/
+ uint8_t reserved_0; /*01h*/
+ uint8_t cmd_status; /*02h*/
+
+ uint8_t reserved_1; /*03h*/
+ uint32_t reserved_2; /*04h*/
+
+ uint32_t context; /*08h*/
+ uint32_t pad_0; /*0Ch*/
+
+ uint16_t flags; /*10h*/
+ uint16_t reserved_3; /*12h*/
+ uint32_t reserved_4; /*14h*/
+
+ uint32_t abort_context; /*18h*/
+ uint32_t pad_1; /*1Ch*/
+
+ uint32_t abort_mfi_phys_addr_lo; /*20h*/
+ uint32_t abort_mfi_phys_addr_hi; /*24h*/
+
+ uint32_t reserved_5[6]; /*28h*/
+
+} __attribute__ ((packed));
+
+struct megasas_smp_frame {
+
+ uint8_t cmd; /*00h*/
+ uint8_t reserved_1; /*01h*/
+ uint8_t cmd_status; /*02h*/
+ uint8_t connection_status; /*03h*/
+
+ uint8_t reserved_2[3]; /*04h*/
+ uint8_t sge_count; /*07h*/
+
+ uint32_t context; /*08h*/
+ uint32_t pad_0; /*0Ch*/
+
+ uint16_t flags; /*10h*/
+ uint16_t timeout; /*12h*/
+
+ uint32_t data_xfer_len; /*14h*/
+
+ uint8_t phy_id; /*18h*/
+ uint8_t port_id; /*19h*/
+ uint8_t connection_rate; /*1Ah*/
+ uint8_t reserved_3; /*1Bh*/
+
+ uint32_t reserved_4; /*1Ch*/
+
+ uint64_t sas_addr; /*20h*/
+
+ union megasas_sgl request_sgl; /*28h*/
+ union megasas_sgl response_sgl;
+
+} __attribute__ ((packed));
+
+union megasas_frame {
+
+ struct megasas_header hdr;
+ struct megasas_init_frame init;
+ struct megasas_io_frame io;
+ struct megasas_pthru_frame pthru;
+ struct megasas_dcmd_frame dcmd;
+ struct megasas_abort_frame abort;
+ struct megasas_smp_frame smp;
+
+ uint8_t raw_bytes[64];
+
+};
+
+struct megasas_cmd;
+
+union megasas_evt_class_locale {
+
+ struct {
+ uint16_t locale;
+ uint8_t reserved;
+ int8_t class;
+ } __attribute__ ((packed)) members;
+
+ uint32_t word;
+
+} __attribute__ ((packed));
+
+struct megasas_evt_log_info {
+ uint32_t newest_seq_num;
+ uint32_t oldest_seq_num;
+ uint32_t clear_seq_num;
+ uint32_t shutdown_seq_num;
+ uint32_t boot_seq_num;
+
+} __attribute__ ((packed));
+
+struct megasas_progress {
+
+ uint16_t progress;
+ uint16_t elapsed_seconds;
+
+} __attribute__ ((packed));
+
+struct megasas_evtarg_ld {
+
+ uint16_t target_id;
+ uint8_t ld_index;
+ uint8_t reserved;
+
+} __attribute__ ((packed));
+
+struct megasas_evtarg_pd {
+ uint16_t device_id;
+ uint8_t encl_index;
+ uint8_t slot_number;
+
+} __attribute__ ((packed));
+
+struct megasas_evt_detail {
+
+ uint32_t seq_num;
+ uint32_t time_stamp;
+ uint32_t code;
+ union megasas_evt_class_locale cl;
+ uint8_t arg_type;
+ uint8_t reserved1[15];
+
+ union {
+ struct {
+ struct megasas_evtarg_pd pd;
+ uint8_t cdb_length;
+ uint8_t sense_length;
+ uint8_t reserved[2];
+ uint8_t cdb[16];
+ uint8_t sense[64];
+ } __attribute__ ((packed)) cdbSense;
+
+ struct megasas_evtarg_ld ld;
+
+ struct {
+ struct megasas_evtarg_ld ld;
+ uint64_t count;
+ } __attribute__ ((packed)) ld_count;
+
+ struct {
+ uint64_t lba;
+ struct megasas_evtarg_ld ld;
+ } __attribute__ ((packed)) ld_lba;
+
+ struct {
+ struct megasas_evtarg_ld ld;
+ uint32_t prevOwner;
+ uint32_t newOwner;
+ } __attribute__ ((packed)) ld_owner;
+
+ struct {
+ uint64_t ld_lba;
+ uint64_t pd_lba;
+ struct megasas_evtarg_ld ld;
+ struct megasas_evtarg_pd pd;
+ } __attribute__ ((packed)) ld_lba_pd_lba;
+
+ struct {
+ struct megasas_evtarg_ld ld;
+ struct megasas_progress prog;
+ } __attribute__ ((packed)) ld_prog;
+
+ struct {
+ struct megasas_evtarg_ld ld;
+ uint32_t prev_state;
+ uint32_t new_state;
+ } __attribute__ ((packed)) ld_state;
+
+ struct {
+ uint64_t strip;
+ struct megasas_evtarg_ld ld;
+ } __attribute__ ((packed)) ld_strip;
+
+ struct megasas_evtarg_pd pd;
+
+ struct {
+ struct megasas_evtarg_pd pd;
+ uint32_t err;
+ } __attribute__ ((packed)) pd_err;
+
+ struct {
+ uint64_t lba;
+ struct megasas_evtarg_pd pd;
+ } __attribute__ ((packed)) pd_lba;
+
+ struct {
+ uint64_t lba;
+ struct megasas_evtarg_pd pd;
+ struct megasas_evtarg_ld ld;
+ } __attribute__ ((packed)) pd_lba_ld;
+
+ struct {
+ struct megasas_evtarg_pd pd;
+ struct megasas_progress prog;
+ } __attribute__ ((packed)) pd_prog;
+
+ struct {
+ struct megasas_evtarg_pd pd;
+ uint32_t prevState;
+ uint32_t newState;
+ } __attribute__ ((packed)) pd_state;
+
+ struct {
+ uint16_t vendorId;
+ uint16_t deviceId;
+ uint16_t subVendorId;
+ uint16_t subDeviceId;
+ } __attribute__ ((packed)) pci;
+
+ uint32_t rate;
+ char str[96];
+
+ struct {
+ uint32_t rtc;
+ uint32_t elapsedSeconds;
+ } __attribute__ ((packed)) time;
+
+ struct {
+ uint32_t ecar;
+ uint32_t elog;
+ char str[64];
+ } __attribute__ ((packed)) ecc;
+
+ uint8_t b[96];
+ uint16_t s[48];
+ uint32_t w[24];
+ uint64_t d[12];
+ } args;
+
+ char description[128];
+
+} __attribute__ ((packed));
+
+struct megasas_instance {
+
+ uint32_t producer;
+ uint32_t consumer;
+
+ uint32_t* reply_queue;
+ dma_addr_t reply_queue_phys_addr;
+
+ dma_addr_t phys_addr;
+
+ unsigned long base_addr;
+ struct megasas_register_set __iomem* reg_set;
+
+ int8_t init_id;
+ uint8_t reserved[3];
+
+ uint16_t max_num_sge;
+ uint16_t max_fw_cmds;
+ uint32_t max_sectors_per_req;
+
+ struct megasas_cmd* cmd_list;
+ struct list_head cmd_pool;
+ spinlock_t cmd_pool_lock;
+ struct dma_pool* frame_dma_pool;
+ struct dma_pool* sense_dma_pool;
+
+ struct megasas_evt_detail evt_detail;
+ struct megasas_cmd* aen_cmd;
+
+ struct Scsi_Host* host;
+ spinlock_t lock;
+ spinlock_t* host_lock;
+
+ wait_queue_head_t int_cmd_wait_q;
+ wait_queue_head_t abort_cmd_wait_q;
+
+ struct pci_dev* pdev;
+ uint32_t unique_id;
+};
+
+/*
+ * Various conversion macros from SCSI command
+ */
+#define SCP2HOST(scp) (scp)->device->host // to host
+#define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata // to soft state
+#define SCP2CHANNEL(scp) (scp)->device->channel // to channel
+#define SCP2TARGET(scp) (scp)->device->id // to target
+#define SCP2LUN(scp) (scp)->device->lun // to LUN
+
+#define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
+#define SCP2ADAPTER(scp) (struct
megasas_instance*)SCSIHOST2ADAP(SCP2HOST(scp))
+
+#define MEGADRV_IS_LOGICAL(scp)
\
+ (SCP2CHANNEL(scp) < MEGADRV_MAX_PD_CHANNELS) ? 0 : 1
+
+#define MEGADRV_DEV_INDEX(inst, scp) \
+ ((SCP2CHANNEL(scp) % 2) * MEGADRV_MAX_DEV_PER_CHANNEL) +
SCP2TARGET(scp)
+
+struct megasas_cmd {
+
+ union megasas_frame* frame;
+ dma_addr_t frame_phys_addr;
+ uint8_t* sense;
+ dma_addr_t sense_phys_addr;
+
+ uint32_t index;
+ uint8_t sync_cmd;
+ uint8_t cmd_status;
+ uint16_t abort_aen;
+
+ struct list_head list;
+ struct scsi_cmnd* scmd;
+ uint32_t frame_count;
+};
+
+#define MAX_MGMT_ADAPTERS 1024
+#define IOC_SIGNATURE "LSILOGIC"
+
+#define IOC_CMD_FIRMWARE 0x0
+#define MR_DRIVER_IOCTL_COMMON 0xF0010000
+#define MR_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
+#define MR_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
+#define MR_DRIVER_IOCTL_MEGARAID_STATISTICS 0xF0010300
+
+#define MR_DRIVER_IOCTL_LINUX 0xF0040000
+#define MR_LINUX_GET_ADAPTER_COUNT (MR_DRIVER_IOCTL_LINUX |
0x0100)
+#define MR_LINUX_GET_ADAPTER_MAP (MR_DRIVER_IOCTL_LINUX |
0x0200)
+#define MR_LINUX_GET_AEN (MR_DRIVER_IOCTL_LINUX |
0x0300)
+
+#define MR_MAX_SENSE_LENGTH 32
+
+struct iocpacket {
+
+ uint16_t version;
+ uint16_t controller_id;
+ uint8_t signature[8];
+ uint32_t reserved_1;
+ uint32_t control_code;
+ uint32_t reserved_2[2];
+ uint8_t frame[64];
+ union megasas_sgl_frame sgl_frame;
+ uint8_t sense_buff[MR_MAX_SENSE_LENGTH];
+ uint8_t data[1];
+
+} __attribute__ ((packed));
+
+struct megasas_mgmt_info {
+
+ uint16_t count;
+ struct megasas_instance* instance[MAX_MGMT_ADAPTERS];
+ uint16_t map[MAX_MGMT_ADAPTERS];
+ int max_index;
+};
+
+struct megasas_drv_ver {
+ uint8_t signature[12];
+ uint8_t os_name[16];
+ uint8_t os_ver[12];
+ uint8_t drv_name[20];
+ uint8_t drv_ver[32];
+ uint8_t drv_rel_date[20];
+
+} __attribute__ ((packed));
+
+#endif /*LSI_MEGARAID_SAS_H*/
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