Arjan van de Ven wrote:
Jeff pointed out several PCI posting errors last time. Before we used udelay and now we changed to readb/readl instead of udelay this time.On Fri, 2005-03-11 at 10:38 -0500, Wen Xiong wrote:
+static void neo_set_cts_flow_control(struct jsm_channel *ch)...
+{
+ u8 ier = readb(&ch->ch_neo_uart->ier);
+ u8 efr = readb(&ch->ch_neo_uart->efr);
+
+
+ writeb(ier, &ch->ch_neo_uart->ier);
+}
Hi,
have you ever audited this driver for PCI posting errors? On very first sight it looks like the driver doesn't do this correctly but it might just be very subtle...
But we only used PCI posting when we think maybe delay there.
So we have to do PCI posting on every writeb? Do you have some rules for doing PCI posting while writeb? depends on what kind of registers?
Thanks, wendy
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