On Mon, Sep 15, 2014 at 07:58:56PM +0800, Shengjiu Wang wrote:
> I add IMX6QDL_CLK_SSIx in this patch, which use share count with
> IMX6QDL_CLK_SSIx_IPG. The SSI driver sound/soc/fsl/fsl_ssi.c will enable
> IMX6QDL_CLK_SSIx_IPG clock in probe, but don't disable it. In the end of
> kernel
> boot up, some one(it is not ssi driver, maybe is the clock tree) will disable
> the IMX6QDL_CLK_SSIx clock, which is not enabled. IMX6QDL_CLK_SSIx_IPG share
> the enable/disable bit with IMX6QDL_CLK_SSIx, So IMX6QDL_CLK_SSIx_IPG is
> disabled, the aplay will fail.
>
> Is this the issue of imx_clk_gate2_shared()? When we want to disable
> IMX6QDL_CLK_SSIx,
> but IMX6QDL_CLK_SSIx_IPG is enabled, can IMX6QDL_CLK_SSIx be disabled?
>
>
> Shawn
>
> How do you think about this?
Shengjiu,
Your analysis is right. I hope the following change will get the shared
gate clock code eventually does the right thing.
Shawn
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 84acdfd1d715..89abdf738dc9 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
struct clk_gate2 *gate = to_clk_gate2(hw);
if (gate->share_count)
- return !!(*gate->share_count);
+ return !!__clk_get_enable_count(hw->clk);
else
return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
}
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