The generic plat_irq_dispatch provided in irq_cpu.c is sufficient for
dispatching interrupts on SEAD-3 in legacy and vectored interrupt modes.
Signed-off-by: Andrew Bresticker <abres...@chromium.org>
Reviewed-by: Qais Yousef <qais.you...@imgtec.com>
Tested-by: Qais Yousef <qais.you...@imgtec.com>
---
No changes from v1.
---
arch/mips/mti-sead3/sead3-int.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c
index cb06cd9..69ae185 100644
--- a/arch/mips/mti-sead3/sead3-int.c
+++ b/arch/mips/mti-sead3/sead3-int.c
@@ -22,32 +22,11 @@
static unsigned long sead3_config_reg;
-asmlinkage void plat_irq_dispatch(void)
-{
- unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
- int irq;
-
- irq = (fls(pending) - CAUSEB_IP - 1);
- if (irq >= 0)
- do_IRQ(MIPS_CPU_IRQ_BASE + irq);
- else
- spurious_interrupt();
-}
-
void __init arch_init_irq(void)
{
- int i;
-
- if (!cpu_has_veic) {
+ if (!cpu_has_veic)
mips_cpu_irq_init();
- if (cpu_has_vint) {
- /* install generic handler */
- for (i = 0; i < 8; i++)
- set_vi_handler(i, plat_irq_dispatch);
- }
- }
-
sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE,
SEAD_CONFIG_SIZE);
gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >>
--
2.1.0.rc2.206.gedb03e5
--
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