Heiko,
On 09/24/2014 01:52 AM, Heiko Stübner wrote:
Am Montag, 22. September 2014, 19:55:16 schrieb jinkun.hong:
From: "jinkun.hong" <jinkun.h...@rock-chips.com>
Signed-off-by: Jack Dai <jack....@rock-chips.com>
Signed-off-by: Wang Caesar <caesar.w...@rock-chips.com>
Signed-off-by: jinkun.hong <jinkun.h...@rock-chips.com>
---
arch/arm/boot/dts/rk3288.dtsi | 45
+++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 3bb5230..714b9d9 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/power-domain/rk3288.h>
#include "skeleton.dtsi"
/ {
@@ -467,6 +468,50 @@
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
};
missing blank line here
Also please mind the ordering. We have the nodes without registers (like the
pinctrl) at the bottom, so maybe add the power-controller alphabetically after
the pinctrl node.
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ rockchip,pmu = <&pmu>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = <RK3288_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
+
+ pd_vio {
+ reg = <RK3288_PD_VIO>;
+ clocks = <&cru HCLK_RGA>, <&cru HCLK_VOP0>,
+ <&cru HCLK_VOP1>, <&cru HCLK_VIO_AHB_ARBI>,
+ <&cru HCLK_VIO_NIU>, <&cru HCLK_VIP>,
+ <&cru HCLK_IEP>, <&cru HCLK_ISP>,
+ <&cru HCLK_VIO2_H2P>, <&cru PCLK_MIPI_DSI0>,
+ <&cru PCLK_MIPI_DSI1>, <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_LVDS_PHY>, <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>, <&cru PCLK_VIO2_H2P>,
+ <&cru ACLK_VOP0>, <&cru ACLK_IEP>,
+ <&cru ACLK_VIO0_NIU>, <&cru ACLK_VIP>,
+ <&cru ACLK_VOP1>, <&cru ACLK_ISP>,
+ <&cru ACLK_VIO1_NIU>, <&cru ACLK_RGA>,
+ <&cru ACLK_RGA_NIU>,<&cru SCLK_RGA>,
+ <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
+ <&cru SCLK_EDP_24M>, <&cru SCLK_EDP>,
+ <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
+ <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+ };
+
+ pd_video {
+ reg = <RK3288_PD_VIDEO>;
+ /* FIXME: add clocks */
what is missing for these clocks? If it's just more clock ids, please
corrdinate with Kever
The clock tree in PD_VIDEO is not complete, maybe because the
MUX which should be set from GRF_SOC_CON0[7].
I will handle this in my patch.
BR
-Kever
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