[PATCH V2 05/15] genirq: Generic chip: Add big endian I/O accessors

[Kevin Cernekee]

Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating
the irqchip.

Signed-off-by: Kevin Cernekee <cerne...@gmail.com>
---
 include/linux/irq.h       |  1 +
 kernel/irq/generic-chip.c | 15 +++++++++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 8049e93..e69b7b2 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -739,6 +739,7 @@ enum irq_gc_flags {
        IRQ_GC_INIT_NESTED_LOCK         = 1 << 1,
        IRQ_GC_MASK_CACHE_PER_TYPE      = 1 << 2,
        IRQ_GC_NO_MASK                  = 1 << 3,
+       IRQ_GC_BE_IO                    = 1 << 4,
 };
 
 /*
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index b2ee65d..c1890bb 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -17,16 +17,27 @@
 static LIST_HEAD(gc_list);
 static DEFINE_RAW_SPINLOCK(gc_lock);
 
+static int is_big_endian(struct irq_chip_generic *gc)
+{
+       return !!(gc->domain->gc->gc_flags & IRQ_GC_BE_IO);
+}
+
 static void irq_reg_writel(struct irq_chip_generic *gc,
                           u32 val, int reg_offset)
 {
-       writel(val, gc->reg_base + reg_offset);
+       if (is_big_endian(gc))
+               iowrite32be(val, gc->reg_base + reg_offset);
+       else
+               writel(val, gc->reg_base + reg_offset);
 }
 
 static u32 irq_reg_readl(struct irq_chip_generic *gc,
                         int reg_offset)
 {
-       return readl(gc->reg_base + reg_offset);
+       if (is_big_endian(gc))
+               return ioread32be(gc->reg_base + reg_offset);
+       else
+               return readl(gc->reg_base + reg_offset);
 }
 
 /**
-- 
2.1.1

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