From: David Daney <david.da...@cavium.com>
The clock divisors are kept in different registers on OCTEON III.
Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.maka...@auriga.com>
---
arch/mips/cavium-octeon/csrc-octeon.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c
b/arch/mips/cavium-octeon/csrc-octeon.c
index b752c4e..d270082 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -18,6 +18,7 @@
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-ipd-defs.h>
#include <asm/octeon/cvmx-mio-defs.h>
+#include <asm/octeon/cvmx-rst-defs.h>
static u64 f;
@@ -39,11 +40,20 @@ void __init octeon_setup_delays(void)
if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
union cvmx_mio_rst_boot rst_boot;
+
rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
rdiv = rst_boot.s.c_mul; /* CPU clock */
sdiv = rst_boot.s.pnr_mul; /* I/O clock */
f = (0x8000000000000000ull / sdiv) * 2;
+ } else if (current_cpu_type() == CPU_CAVIUM_OCTEON3) {
+ union cvmx_rst_boot rst_boot;
+
+ rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
+ rdiv = rst_boot.s.c_mul; /* CPU clock */
+ sdiv = rst_boot.s.pnr_mul; /* I/O clock */
+ f = (0x8000000000000000ull / sdiv) * 2;
}
+
}
/*
--
2.1.3
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