I figured I should send this email before I forget about this issue: If you run perf record across any EFI mixed mode call or otherwise receive an NMI or MCE, the machine triple-faults. The cause is straightforward: there is no valid IDT when we have long mode disabled for the duration of the EFI call.
As far as I know, the only way to have continuously functional interrupt handling across a long mode transition is to install an interrupt vector table and hope that CPUs actually do something intelligent when receiving an interrupt with LME=1, LMA=1, and PG=0. Yuck. Could we get away with issuing 32-bit EFI calls in compat mode, i.e. with a 32-bit CPL0 CS but while still in long mode? I think that delivery of an IST interrupt (which includes both NMI and MCE) will correctly switch to a fully valid 64-bit state and would correctly switch back when we execute IRET at the end. (Am I missing some reason that switching bitness without a privilege level change doesn't work well? I haven't thought of anything, other than the lack of SS controls on intra-ring interrupts, but that shouldn't be an issue here.) As an added benefit, this would considerably simplify the code. --Andy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
