On 31.12.2014 09:57, Jisheng Zhang wrote:
The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.
Signed-off-by: Jisheng Zhang <jszh...@marvell.com>
Cc: sta...@vger.kernel.org # 3.16+
---
drivers/clk/berlin/bg2q.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 21784e4..440ef81 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -285,7 +285,6 @@ static const struct berlin2_gate_data bg2q_gates[]
__initconst = {
{ "pbridge", "perif", 15, CLK_IGNORE_UNUSED },
{ "sdio", "perif", 16, CLK_IGNORE_UNUSED },
{ "nfc", "perif", 18 },
- { "smemc", "perif", 19 },
Jisheng,
if bit 19 is for nfc, how does that work out with bit 18 which is
still assigned to nfc? Can you re-evaluate clkenable registers for
BG2Q and fix it up accordingly? I'd suggest to still disable as many
clocks as possible rather than removing the corresponding clk_gates.
Sebastian
{ "pcie", "perif", 22 },
};
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
