On Fri, 2015-01-09 at 14:37 +0800, Wang Nan wrote:
> This patch introduce kprobeopt for ARM 32.
>
> Limitations:
> - Currently only kernel compiled with ARM ISA is supported.
>
> - Offset between probe point and optinsn slot must not larger than
> 32MiB. Masami Hiramatsu suggests replacing 2 words, it will make
> things complex. Futher patch can make such optimization.
>
> Kprobe opt on ARM is relatively simpler than kprobe opt on x86 because
> ARM instruction is always 4 bytes aligned and 4 bytes long. This patch
> replace probed instruction by a 'b', branch to trampoline code and then
> calls optimized_callback(). optimized_callback() calls opt_pre_handler()
> to execute kprobe handler. It also emulate/simulate replaced instruction.
>
> When unregistering kprobe, the deferred manner of unoptimizer may leave
> branch instruction before optimizer is called. Different from x86_64,
> which only copy the probed insn after optprobe_template_end and
> reexecute them, this patch call singlestep to emulate/simulate the insn
> directly. Futher patch can optimize this behavior.
>
> Signed-off-by: Wang Nan <[email protected]>
> Acked-by: Masami Hiramatsu <[email protected]>
> Cc: Jon Medhurst (Tixy) <[email protected]>
> Reviewed-by: Jon Medhurst (Tixy) <[email protected]>
> Cc: Russell King - ARM Linux <[email protected]>
> Cc: Will Deacon <[email protected]>
> ---
[...]
> +asm (
> + ".global optprobe_template_entry\n"
> + "optprobe_template_entry:\n"
> + ".global optprobe_template_sub_sp\n"
> + "optprobe_template_sub_sp:"
> + " sub sp, sp, #0xff\n"
> + " stmia sp, {r0 - r14} \n"
> + ".global optprobe_template_add_sp\n"
> + "optprobe_template_add_sp:"
> + " add r3, sp, #0xff\n"
> + " str r3, [sp, #52]\n"
> + " mrs r4, cpsr\n"
> + " str r4, [sp, #64]\n"
> + " mov r1, sp\n"
> + " ldr r0, 1f\n"
> + " ldr r2, 2f\n"
> + /*
> + * AEABI requires an 8-bytes alignment stack. If
> + * SP % 8 != 0 (SP % 4 == 0 should be ensured),
> + * alloc more bytes here.
> + */
> + " and r4, sp, #4\n"
> + " sub sp, sp, r4\n"
> +#if __LINUX_ARM_ARCH__ >= 5
> + " blx r2\n"
> +#else
> + " mov lr, pc\n"
> + " bx r2\n"
I think the BX instruction is not supported for ARMv4 chips that don't
have Thumb support (e.g. SA110), at least an old ARM ARM I have says BX
is supported on "Version 5 and above, and T variants of version 4".
Though building assabet_defconfig with kprobes enabled doesn't produce
an error for the BX instruction (!?)
To be safe I would be tempted to use "mov pc, r2" instead. Again, if you
agree, I'll change this in the patch in the branch I'm putting together.
[...]
--
Tixy
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