On Sat, Jan 10, 2015 at 9:17 PM, Andy Lutomirski <[email protected]> wrote: >> After I've seen the disassembly I myself posted, I can't help but wonder >> why we use 5-byte instructions to store and load regs on stack when >> pushes and pops are 1 or 2-byte long. > > I asked this once, and someone told me that push/pop has lower > throughput. I find this surprising.
Theoretically yes. In practice, AMD K7 and K8 seem to be able to execute two movq's in one cycle, but only one push. For all other processors I looked at, they have the same throughput: K10 can do two movq's in one cycle, but also two push'es. Bulldozer...Steamroller: can do one insn per cycle. Bobcat..Jaguar: can do one insn per cycle. Core 2: can do one insn per cycle. Nehalem: can do one insn per cycle. The above was microbenchmarked with long sequences of similar instructions, in which case store unit gets saturated and becomes a bottleneck. Here's the document. http://www.agner.org/optimize/instruction_tables.pdf -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
