> > This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has > following memory buses to translate data between DRAM and eMMC/sub-IPs. > > Following list specifies the detailed relation between memory bus clock and > DMC > IP in MIF (Memory Interface) block: > - DMC clock : DMC (Dynamic Memory Controller) > > Following list specifies the detailed relation between memory bus clock and > sub-IPs in INT (Internal) block: > - ACLK100 clock : PERIL > - ACLK160 clock : LCD0 > - ACLK200 clock : FSYS > - ACLK266 clock : ISP > - GDL/GDR clock : leftbus/rightbus > - SCLK_MFC clock : MFC > > Cc: Kukjin Kim <[email protected]> > Cc: Myungjoo Ham <[email protected]> > Cc: Kyungmin Park <[email protected]> > Signed-off-by: Chanwoo Choi <[email protected]> > Acked-by: Kyungmin Park <[email protected]>
Acked-by: MyungJoo Ham <[email protected]> > --- > arch/arm/boot/dts/exynos3250.dtsi | 125 > ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 125 insertions(+) > N�����r��y����b�X��ǧv�^�){.n�+����{����zX����ܨ}���Ơz�&j:+v�������zZ+��+zf���h���~����i���z� �w���?�����&�)ߢf��^jǫy�m��@A�a��� 0��h���i
