> > This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has > one memory bus to translate data between DRAM and eMMC/sub-IPs because > Exynos4210 must need only one regulator for memory bus. > > Following list specifies the detailed relation between memory bus clock and > sub-IPs: > - DMC/ACP clock : DMC (Dynamic Memory Controller) > - ACLK200 clock : LCD0 > - ACLK100 clock : PERIL/PERIR/MFC(PCLK) > - ACLK160 clock : CAM/TV/LCD0/LCD1 > - ACLK133 clock : FSYS/GPS > - GDL/GDR clock : leftbus/rightbus > - SCLK_MFC clock : MFC > > Cc: Kukjin Kim <[email protected]> > Cc: Myungjoo Ham <[email protected]> > Cc: Kyungmin Park <[email protected]> > Signed-off-by: Chanwoo Choi <[email protected]>
Acked-by: MyungJoo Ham <[email protected]> Revisiting good old days..? (good to see the first busfreq driver experimented with is being DT-nized... :) ) Cheers, MyungJoo
