On Wed, Jan 21, 2015 at 4:18 PM, Zhang, Yang Z <yang.z.zh...@intel.com> wrote: > Wincy Van wrote on 2015-01-16: >> To enable nested apicv support, we need per-cpu vmx control MSRs: >> 1. If in-kernel irqchip is enabled, we can enable nested >> posted interrupt, we should set posted intr bit in the >> nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled, >> we can not enable nested posted interrupt, the posted intr bit in >> the nested_vmx_pinbased_ctls_high will be cleared. >> Since there would be different settings about in-kernel irqchip >> between VMs, different nested control MSRs are needed. > > I'd suggest you to check irqchip_in_kernel() instead moving the whole ctrl > msr to per vcpu. >
Yes, moving that msrs looks a bit ugly, but the irqchip_in_kernel is per-VM, not a global setting, there would be different settings of kernel_irqchip between VMs. If we use irqchip_in_kernel to check it and set different value of the ctl msrs, I think it may be even worse than moving the msrs, because this logic should be a init function, and this setting should be converged. Thanks, Wincy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
