We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.

Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>

---
v2: no change
v3: no change

 arch/powerpc/kernel/head_8xx.S | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index e803ad0..ead6448 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -309,7 +309,7 @@ SystemCall:
 
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
-       mtspr   SPRN_DAR, r3
+       mtspr   SPRN_SPRG_SCRATCH2, r3
 #endif
        EXCEPTION_PROLOG_0
 
@@ -362,8 +362,7 @@ InstructionTLBMiss:
 
        /* Restore registers */
 #ifdef CONFIG_8xx_CPU6
-       mfspr   r3, SPRN_DAR
-       mtspr   SPRN_DAR, r11   /* Tag DAR */
+       mfspr   r3, SPRN_SPRG_SCRATCH2
 #endif
        EXCEPTION_EPILOG_0
        rfi
@@ -371,7 +370,7 @@ InstructionTLBMiss:
        . = 0x1200
 DataStoreTLBMiss:
 #ifdef CONFIG_8xx_CPU6
-       mtspr   SPRN_DAR, r3
+       mtspr   SPRN_SPRG_SCRATCH2, r3
 #endif
        EXCEPTION_PROLOG_0
        mfcr    r10
@@ -441,7 +440,7 @@ DataStoreTLBMiss:
 
        /* Restore registers */
 #ifdef CONFIG_8xx_CPU6
-       mfspr   r3, SPRN_DAR
+       mfspr   r3, SPRN_SPRG_SCRATCH2
 #endif
        mtspr   SPRN_DAR, r11   /* Tag DAR */
        EXCEPTION_EPILOG_0
-- 
2.1.0

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