On Fri, Feb 20, 2015 at 1:15 AM, Dinh Nguyen <dinh.li...@gmail.com> wrote: > Hi Rob, > > On 2/19/15 12:13 PM, Rob Herring wrote: >> On Thu, Feb 19, 2015 at 11:06 AM, <dingu...@opensource.altera.com> wrote: >>> From: Dinh Nguyen <dingu...@opensource.altera.com> >>> >>> By not having bit 22 set in the PL310 Auxiliary Control register (shared >>> attribute override enable) has the side effect of transforming Normal >>> Shared Non-cacheable reads into Cacheable no-allocate reads. >>> >>> Coherent DMA buffers in Linux always have a Cacheable alias via the >>> kernel linear mapping and the processor can speculatively load cache >>> lines into the PL310 controller. With bit 22 cleared, Non-cacheable >>> reads would unexpectedly hit such cache lines leading to buffer >>> corruption. >> >> You really should be doing this in your bootloader. >> > > Can I ask what is your reasoning for doing this in the bootloader? It's > seems like this is such a nice mechanism to do it here.
Primarily, this register is secure only and we try to avoid secure mode setup in the kernel. Russell also has had a patch to do this generically in his patch queue forever. If we want this in the kernel, then we should apply that. Rob -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
