On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote: > The NDDB register holds the data that are needed by the read and write > commands. > > However, during a read PIO access, the datasheet specifies that after each 32 > bytes read in that register, when BCH is enabled, we have to make sure that > the > RDDREQ bit is set in the NDSR register. > > This fixes an issue that was seen on the Armada 385, and presumably other > mvebu > SoCs, when a read on a newly erased page would end up in the driver reporting > a > timeout from the NAND. > > Cc: <sta...@vger.kernel.org> # v3.14 > Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Pushed this one to linux-mtd.git. I'll try to get it out in the 4.0 cycle. I assume patch 2 (the DT addition) will go through arm-soc. Brian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
