instead of round_rate, so we can take rate constraints into account when
choosing the best rate.
Signed-off-by: Tomeu Vizoso <tomeu.viz...@collabora.com>
---
drivers/clk/tegra/clk-emc.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
index 704fff7..615da43 100644
--- a/drivers/clk/tegra/clk-emc.c
+++ b/drivers/clk/tegra/clk-emc.c
@@ -117,8 +117,11 @@ static unsigned long emc_recalc_rate(struct clk_hw *hw,
* safer since things have EMC rate floors. Also don't touch parent_rate
* since we don't want the CCF to play with our parent clocks.
*/
-static long emc_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static long emc_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long min_rate,
+ unsigned long max_rate,
+ unsigned long *best_parent_rate,
+ struct clk_hw **best_parent_hw)
{
struct tegra_clk_emc *tegra;
u8 ram_code = tegra_read_ram_code();
@@ -133,7 +136,15 @@ static long emc_round_rate(struct clk_hw *hw, unsigned
long rate,
timing = tegra->timings + i;
- if (timing->rate >= rate)
+ if (timing->rate > max_rate) {
+ i = min(i, 1);
+ return tegra->timings[i - 1].rate;
+ }
+
+ if (timing->rate < min_rate)
+ continue;
+
+ if (timing->rate >= rate)
return timing->rate;
}
@@ -452,7 +463,7 @@ static int load_timings_from_dt(struct tegra_clk_emc *tegra,
static const struct clk_ops tegra_clk_emc_ops = {
.recalc_rate = emc_recalc_rate,
- .round_rate = emc_round_rate,
+ .determine_rate = emc_determine_rate,
.set_rate = emc_set_rate,
.get_parent = emc_get_parent,
};
--
2.1.0
--
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