We need to round the calculated value to have it match the requested rate.
While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we
will need it in later patches for set_rate.
And let's remove two unused includes.
Cc: Brian Hutchinson <b.hutch...@gmail.com>
Cc: Matthijs van Duin <matthijsvand...@gmail.com>
Cc: Tero Kristo <t-kri...@ti.com>
Signed-off-by: Tony Lindgren <t...@atomide.com>
---
drivers/clk/ti/fapll.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index d216406..3b5e231 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -11,12 +11,10 @@
#include <linux/clk-provider.h>
#include <linux/delay.h>
-#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
-#include <asm/div64.h>
/* FAPLL Control Register PLL_CTRL */
#define FAPLL_MAIN_LOCK BIT(7)
@@ -49,6 +47,8 @@
/* Synthesizer frequency register */
#define SYNTH_LDFREQ BIT(31)
+#define SYNTH_MAX_DIV_M 0xff
+
struct fapll_data {
struct clk_hw hw;
void __iomem *base;
@@ -218,11 +218,10 @@ static unsigned long ti_fapll_synth_recalc_rate(struct
clk_hw *hw,
rate *= 8;
}
- /* Synth ost-divider M */
- synth_div_m = readl_relaxed(synth->div) & 0xff;
- do_div(rate, synth_div_m);
+ /* Synth post-divider M */
+ synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
- return rate;
+ return DIV_ROUND_UP_ULL(rate, synth_div_m);
}
static struct clk_ops ti_fapll_synt_ops = {
--
2.1.4
--
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