On Mon, Mar 30, 2015 at 10:55:46AM -0700, Joe Perches wrote:
> On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote:
> > This patch adds common clock support for Mediatek SoCs, including plls,
> > muxes and clock gates.
>
> trivia:
>
> > diff --git a/drivers/clk/mediatek/clk-gate.c
> > b/drivers/clk/mediatek/clk-gate.c
>
> > +static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
> > +{
> []
> > + return val == 0;
> > +}
> > +
> > +static int mtk_cg_bit_is_set(struct clk_hw *hw)
> > +{
> []
> > + return val != 0;
> > +}
>
> These functions may be better returning a bool
The return type of these functions is forced by function prototype in
struct clk_ops.
Sascha
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