[PATCH v2 6/7] clk: tegra: switch to clk_div_mask()

[Andy Shevchenko]

Convert the code to use clk_div_mask() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
---
 drivers/clk/tegra/clk-divider.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 59a5714..d23dbc1 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -24,9 +24,8 @@
 #include "clk.h"
 
 #define pll_out_override(p) (BIT((p->shift - 6)))
-#define div_mask(d) ((1 << (d->width)) - 1)
 #define get_mul(d) (1 << d->frac_width)
-#define get_max_div(d) div_mask(d)
+#define get_max_div(d) clk_div_mask(d->width)
 
 #define PERIPH_CLK_UART_DIV_ENB BIT(24)
 
@@ -73,7 +72,7 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw 
*hw,
        u64 rate = parent_rate;
 
        reg = readl_relaxed(divider->reg) >> divider->shift;
-       div = reg & div_mask(divider);
+       div = reg & clk_div_mask(divider->width);
 
        mul = get_mul(divider);
        div += mul;
@@ -120,7 +119,7 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, 
unsigned long rate,
                spin_lock_irqsave(divider->lock, flags);
 
        val = readl_relaxed(divider->reg);
-       val &= ~(div_mask(divider) << divider->shift);
+       val &= ~(clk_div_mask(divider->width) << divider->shift);
        val |= div << divider->shift;
 
        if (divider->flags & TEGRA_DIVIDER_UART) {
-- 
2.1.4

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