if using you patch, the "synchronized TSC with CPU" never come out.
then with your patch, I add back patch that moving set callin_map from smp_callin to start_secondary. It told me can not inquire the apic for the CPU 1....2.... YH Initializing CPU#1 masked ExtINT on CPU#1 Calibrating delay using timer specific routine.. 3600.30 BogoMIPS (lpj=7200601) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) CPU 1(2) -> Node 0 -> Core 1 stepping 02 CPU 1: Syncing TSC to CPU 0. CPU 1: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 1415 cycles) On 7/28/05, Eric W. Biederman <[EMAIL PROTECTED]> wrote: > yhlu <[EMAIL PROTECTED]> writes: > > > I have some problem with this patch. > > > > YH > > > > On 7/28/05, yhlu <[EMAIL PROTECTED]> wrote: > >> Do you mean solve the timing problem for 2 way dual core or 4 way > >> single core above? > > As best as I can determine the problem is possible any time > you have more than 2 cpus (from the kernels perspective), > but you have ti hit a fairly narrow window in cpu start up. > > What problem do you have with this patch. > > Eric > - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
