From: Eric Nelson <eric.nel...@boundarydevices.com>

3.4.107-rc1 review patch.  If anyone has any objections, please let me know.

------------------


commit 58cc9c9a175885bbf6bae3acf18233d0a8229a84 upstream.

To quote from section 1.3.1 of the data sheet:
        The SGTL5000 has an internal reset that is deasserted
        8 SYS_MCLK cycles after all power rails have been brought
        up. After this time, communication can start

        ...
        1.0us represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK.

Signed-off-by: Eric Nelson <eric.nel...@boundarydevices.com>
Reviewed-by: Fabio Estevam <fabio.este...@freescale.com>
Signed-off-by: Mark Brown <broo...@kernel.org>
Signed-off-by: Zefan Li <lize...@huawei.com>
---
 sound/soc/codecs/sgtl5000.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index c40b7ca..87cbf14 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -1238,6 +1238,9 @@ static int sgtl5000_enable_regulators(struct 
snd_soc_codec *codec)
        /* wait for all power rails bring up */
        udelay(10);
 
+       /* Need 8 clocks before I2C accesses */
+       udelay(1);
+
        /* read chip information */
        reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
        if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
-- 
1.9.1

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