Quoting Sergej Sawazki (2015-05-11 01:44:19) > The second synthesis stage in the Si5351 clock generator consists of six > *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* > dividers (MS6 and MS7). The current si5351 driver implementation does > not handle MS6 and MS7 correctly, this leads to wrong rates on output 6 > and 7. This patch series fixes that. > > Patch 1 fixes the divider calculation for multisynth 6 and 7. > > Patch 2 fixes the divider re-calculation for multisynth 6 and 7. > > Info: Base on branch 'clk-fixes'. > > Sergej Sawazki (2): > clk: si5351: fix .round_rate for multisynth 6-7 > clk: si5351: fix .recalc_rate for multisynth 6-7
Applied both patches to clk-next. Regards, Mike > > drivers/clk/clk-si5351.c | 26 +++++++++++++++++++------- > 1 file changed, 19 insertions(+), 7 deletions(-) > > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
