From: Joerg Roedel <[email protected]>

QI needs to be available when we write the root entry into
hardware because flushes might be necessary after this.

Signed-off-by: Joerg Roedel <[email protected]>
---
 drivers/iommu/intel-iommu.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 14af51d..b380fd1 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -2783,6 +2783,8 @@ static int __init init_dmars(void)
        for_each_active_iommu(iommu, drhd) {
                g_iommus[iommu->seq_id] = iommu;
 
+               intel_iommu_init_qi(iommu);
+
                ret = iommu_init_domains(iommu);
                if (ret)
                        goto free_iommu;
@@ -2799,9 +2801,6 @@ static int __init init_dmars(void)
                        hw_pass_through = 0;
        }
 
-       for_each_active_iommu(iommu, drhd)
-               intel_iommu_init_qi(iommu);
-
        if (iommu_pass_through)
                iommu_identity_mapping |= IDENTMAP_ALL;
 
-- 
1.9.1

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