Hi Will, On Tuesday 23 June 2015 02:19 PM, Will Deacon wrote: >> +/* >> > + * MMIO can also get buffered/optimized in micro-arch, so barriers needed >> > + * Based on ARM model for the typical use case >> > + * >> > + * <writel_relaxed DMA buffer> >> > + * <writel MMIO "go" reg> >> > + * or: >> > + * <readl MMIO "status" reg> >> > + * <readl_relaxed DMA buffer> > The writel_relaxed/readl_relaxed parts here would actually just be > bog-standard loads and stores to an in-memory buffer. I was trying too hard > to show the barrier semantics and accidentally turned the DMA buffers into > __iomem regions.
Not sure if I follow you completely :-) IMHO, It doesn't matter if we are dealing with a typical DMA buffer (cached) or a buffer descriptor (typically uncached unless there's hardware IO-coh or some such). Both the cases assume a vanilla ld/st to buffer (using relaxed API) with a surrounding MMIO access. > > If you fix the comment: Does this look better ? - * <writel_relaxed DMA buffer> + * <writel_relaxed DMA buffer (cached or uncached)> > > Reviewed-by: Will Deacon <will.dea...@arm.com> > > Sorry for messing you about. NP. -Vineet -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
