On 02/07/15 15:53, Boris Ostrovsky wrote: > Map shared data structure that will hold CPU registers, VPMU context, > V/PCPU IDs of the CPU interrupted by PMU interrupt. Hypervisor fills > this information in its handler and passes it to the guest for further > processing. > > Set up PMU VIRQ. > > Now that perf infrastructure will assume that PMU is available on a PV > guest we need to be careful and make sure that accesses via RDPMC > instruction don't cause fatal traps by the hypervisor. Provide a nop > RDPMC handler. > > For the same reason avoid issuing a warning on a write to APIC's LVTPC. > > Both of these will be made functional in later patches. [...] > + rc = bind_virq_to_irqhandler(VIRQ_XENPMU, cpu, > + xen_pmu_irq_handler, > + IRQF_PERCPU|IRQF_NOBALANCING, > + pmu_name, NULL);
If you bind a VIRQ as IRQF_PERCPU it can only be safely unbound on the CPU it is bound to (because the percpu handler does not take the desc->lock). Otherwise, Reviewed-by: David Vrabel <[email protected]> David -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
