* Roger Quadros <rog...@ti.com> [150512 09:08]:
> This register is required to be passed to the SATA PHY driver
> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
> 
> Signed-off-by: Roger Quadros <rog...@ti.com>
> Signed-off-by: Sekhar Nori <nsek...@ti.com>
> ---
>  arch/arm/boot/dts/dra7.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index f03a091..260f300 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -1135,6 +1135,7 @@
>                               ctrl-module = <&omap_control_sata>;
>                               clocks = <&sys_clkin1>, <&sata_ref_clk>;
>                               clock-names = "sysclk", "refclk";
> +                             syscon-pllreset = <&dra7_ctrl_core 0x3fc>;
>                               #phy-cells = <0>;
>                       };
>  

Looks like this one is still pending driver changes, please
resend when those are resolved. I'll untag this one for now.

Regards,

Tony
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