On Fri, Jul 17, 2015 at 4:31 PM, Andi Kleen <a...@linux.intel.com> wrote:
> On Fri, Jul 17, 2015 at 03:00:18PM -0700, Stephane Eranian wrote:
>> Andi,
>>
>> On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen <a...@linux.intel.com> wrote:
>> >> But then, the SDM is misleading. It is not describing what's
>> >> implemented for SKL.
>> >
>> > Actually it has a list of valid values you can put into the various fields.
>> > None of them have the bits set you're trying to set.
>> >
>> You are talking about the events (bit 0-7). I am talking about the bubble
>> thresholds. I am okay with the event list for bits 0-7.
>
> Fair enough. There's a one-off in the MSR table and table 18-54. The IDQ
> bubble width is only 21:20. I'll ask for that to be fixed in both places
> that document them.
>
There is still something broken here, if bit 22 is not implemented,
then you have
a bunch of frontend events in the SKL event table (download.01.org) which are
bogus:
{
"EventCode": "0xC6",
"UMask": "0x01",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"BriefDescription": "Retired instructions that are fetched after
an interval where the front-end delivered no uops for a period of 8
cycles which was not interrupted by a back-end stall.",
"PublicDescription": "Retired instructions that are fetched after
an interval where the front-end delivered no uops for a period of 8
cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"SampleAfterValue": "100007",
"MSRIndex": "0x3F7",
"MSRValue": "0x400806", <=========
....
},
{
"EventCode": "0xC6",
"UMask": "0x01",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"BriefDescription": "Retired instructions that are fetched after
an interval where the front-end delivered no uops for a period of 16
cycles which was not interrupted by a back-end stall.",
"PublicDescription": "Retired instructions that are fetched after
an interval where the front-end delivered no uops for a period of 16
cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"SampleAfterValue": "100007",
"MSRIndex": "0x3F7",
"MSRValue": "0x401006", <=====
...
},
{
"EventCode": "0xC6",
"UMask": "0x01",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"BriefDescription": "Retired instructions that are fetched after
an interval where the front-end delivered no uops for a period of 32
cycles which was not interrupted by a back-end stall.",
"PublicDescription": "Retired instructions that are fetched after
an interval where the front-end delivered no uops for a period of 32
cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"SampleAfterValue": "100007",
"MSRIndex": "0x3F7",
"MSRValue": "0x402006", <=========
...
},
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