Commit-ID:  0f29e573dd32bb8598e74271454e97c962da5e05
Gitweb:     http://git.kernel.org/tip/0f29e573dd32bb8598e74271454e97c962da5e05
Author:     Andi Kleen <[email protected]>
AuthorDate: Sun, 10 May 2015 12:22:47 -0700
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 4 Aug 2015 10:16:58 +0200

perf/x86/intel: Move PMU ACK to after LBR read

With Arch Perfmon v4 the PMU ack unfreezes the LBRs. So we need to do
the PMU ack after the LBR reading, otherwise the LBRs would be polluted
by the PMI handler.

This is a minimal change. In principle the ACK could be moved much later.

Signed-off-by: Andi Kleen <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Link: 
http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c 
b/arch/x86/kernel/cpu/perf_event_intel.c
index 52c9ded..da93b4b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1594,6 +1594,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
 
        loops = 0;
 again:
+       intel_pmu_lbr_read();
        intel_pmu_ack_status(status);
        if (++loops > 100) {
                static bool warned = false;
@@ -1608,7 +1609,6 @@ again:
 
        inc_irq_stat(apic_perf_irqs);
 
-       intel_pmu_lbr_read();
 
        /*
         * Ignore a range of extra bits in status that do not indicate
--
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