On Sun, Aug 23, 2015 at 4:26 AM, Ingo Molnar <mi...@kernel.org> wrote:
>
> * Andy Lutomirski <l...@kernel.org> wrote:
>
>> It's statically initialized, so we don't need to dynamically
>> initialize it too.
>>
>> Reported-by: Brian Gerst <brge...@gmail.com>
>> Signed-off-by: Andy Lutomirski <l...@kernel.org>
>> ---
>>
>> Changes since v1: Delete the code :)
>>
>> arch/x86/kernel/cpu/common.c | 8 --------
>>  1 file changed, 8 deletions(-)
>>
>> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
>> index e2ed2513a51e..e08eee98a5f8 100644
>> --- a/arch/x86/kernel/cpu/common.c
>> +++ b/arch/x86/kernel/cpu/common.c
>> @@ -1005,14 +1005,6 @@ void enable_sep_cpu(void)
>>       if (IS_ENABLED(CONFIG_X86_32) && !boot_cpu_has(X86_FEATURE_SEP))
>>               goto out;
>>
>> -#ifdef CONFIG_X86_32
>> -     /*
>> -      * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
>> -      * see the big comment in struct x86_hw_tss's definition.
>> -      */
>> -     tss->x86_tss.ss1 = __KERNEL_CS;
>> -#endif
>> -
>>       wrmsrl_safe(MSR_IA32_SYSENTER_CS, __KERNEL_CS);
>>       wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
>>                   (unsigned long)tss +
>
> So this code changed substantially in tip:x86/asm - do we still need this 
> patch?
>

Yes, although I think it's actually the other way around -- I think
this patch may have applied on top of something that never made it
into tip/x86/asm.  I can re-check or I could just rebase the patch (or
you could apply it with the obvious fixup).

It's obviously not a critical fix.

--Andy
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