On Thu, 20 Aug 2015, Matt Redfearn wrote: > The mask cache must be initialised in the generic IRQ chip, > otherwise enabling one channel will actually enable all > channels when the empty mask cache is written. > > Signed-off-by: Matt Redfearn <[email protected]> > --- > drivers/mfd/jz4740-adc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-)
Applied, thanks. > diff --git a/drivers/mfd/jz4740-adc.c b/drivers/mfd/jz4740-adc.c > index ae2ad8ad0e2f..e8699c0cdae6 100644 > --- a/drivers/mfd/jz4740-adc.c > +++ b/drivers/mfd/jz4740-adc.c > @@ -276,7 +276,8 @@ static int jz4740_adc_probe(struct platform_device *pdev) > ct->chip.irq_unmask = irq_gc_mask_clr_bit; > ct->chip.irq_ack = irq_gc_ack_set_bit; > > - irq_setup_generic_chip(gc, IRQ_MSK(5), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); > + irq_setup_generic_chip(gc, IRQ_MSK(5), IRQ_GC_INIT_MASK_CACHE, 0, > + IRQ_NOPROBE | IRQ_LEVEL); > > adc->gc = gc; > -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
