On Fri, Sep 04, 2015 at 12:11:51AM +0600, Alexander Kuleshov wrote: > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -28,7 +28,50 @@ > > #define ARM64_NCAPS 4 > > +/* > + * ID_AA64ISAR0_EL1 AES, bits [7:4] > + */ > +#define ID_AA64ISAR0_EL1_AES_MASK 4 > +#define ID_AA64ISAR0_EL1_AES(feature) \ > + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 1UL)
This looks more like a shift than a mask. I don't think it's worth defining another macro for the shift. > +#define ID_AA64ISAR0_EL1_PMULL(feature) \ > + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 2UL) I'm not against some clean-up here but I think you break the original logic. AES and PMULL are not exclusive, the latter implies the former but the way you check here is just individual bits. These id fields are meant to be treated as 4-bit signed values, so if AES means >= 1, PMULL means >= 2. We have a cpuid_feature_extract_field() (in linux-next and about to go in 4.3-rc1), so use this one for extracting the signed 4-bit field. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
