In Berlin SoCs, there are two kinds of cpu reset control registers: the first one's corresponding bits will be self-cleared after some cycles, while the second one's bits won't. Previously the first kind of reset control register is used, this patch uses the second kind one to prepare for the next hotplug commit.
Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- arch/arm/mach-berlin/platsmp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c index 34a3753..bde327b 100644 --- a/arch/arm/mach-berlin/platsmp.c +++ b/arch/arm/mach-berlin/platsmp.c @@ -17,7 +17,7 @@ #include <asm/smp_plat.h> #include <asm/smp_scu.h> -#define CPU_RESET 0x00 +#define CPU_RESET 0x20 #define RESET_VECT 0x00 #define SW_RESET_ADDR 0x94 @@ -31,6 +31,8 @@ static inline void berlin_perform_reset_cpu(unsigned int cpu) u32 val; val = readl(cpu_ctrl + CPU_RESET); + val &= ~BIT(cpu_logical_map(cpu)); + writel(val, cpu_ctrl + CPU_RESET); val |= BIT(cpu_logical_map(cpu)); writel(val, cpu_ctrl + CPU_RESET); } -- 2.5.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/