Jeff Garzik <[EMAIL PROTECTED]> writes: >>> We are referring to the standard PCI 2.2 bit, PCI_COMMAND_INTX_DISABLE. >> Yeah, I figured it, I somewhat forgot about it ... it got introduced >> in >> 2.3 though, no ? > > It's pretty new. 2.2 or 2.3.
2.3. PCI 2.2 defines bits 0-9 only (bit 7 = Stepping Control) PCI 2.3 and 3.0: bit 7 = Reserved, bit 10 = Interrupt Disable. OTOH many devices have "interrupt disable" bit somewhere else, in their specific PCI config registers or in regular config registers (accessible with normal Memory Read/Write cycles). MSI was first defined in PCI 2.2. Perhaps I can check NV (MCP55) for that problem with a module claiming all free interrupts. Tomorrow maybe. -- Krzysztof Halasa - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/